1. Field of the Invention
The present invention relates to a hierarchical routing method and a medium on which the hierarchical routing program is stored, and more particularly, to a hierarchical routing method to be implemented in a layout system for a semiconductor integrated circuit having a repetitive circuit portion.
2. Description of the Related Art
Recently, digital signal processors (DSPs) have been utilized for multiple purposes in systems for performing radio and other communications or handling moving pictures. In the DSP, when realizing a semiconductor integrated circuit, approximately 90% of the internal configuration is a repetitive circuit referred to as a data path. When a computer uses multimedia, it is desirable to design a high-performance data path within a short period of time.
In the past, there have been two methods of laying out circuit elements for constructing a repetitive circuit portion (data path) of a DSP, arithmetic logic unit (ALU), multiplier (tree circuit) or the like; that is, a method of laying them out completely manually and a method using a completely automated placement/routing system (automatic routing system).
Concretely, for example, when emphasis is put on properties, a repetitive circuit portion is designed by repeatedly placing a unit of layout that is the smallest wiring produced manually (a unit circuit that is a cell). However, the wiring in the repetitive circuit portion includes not only a regular repetition pattern but also many irregular patterns.
In order to produce the whole wiring manually, many man-hours are required. Moreover, an operator producing the wiring often makes mistakes. This causes a prolonged (delayed) design process.
Incidentally, an automatic placement/routing system is used to design a random circuit (random logic) originally devoid of regularity. A system for placing a cell (unit circuit) used to construct the same circuit at the same relative position for the purpose of designing a repetitive circuit portion has been proposed in the past.
However, the automatic placement/routing system carries out routing independently according to a maze routing method or the like. In a cell used to construct each repetitive circuit portion, circuit elements are laid out so that a total length of a resultant wiring becomes the shortest. This poses a problem that the length of a wiring becomes different among the cells constituting a repetitive circuit portion.
A design tool dedicated to a data path (repetitive circuit portion) has been developed by producing an automatic placement/routing tool dedicated to random circuits. The tool merely gives control so as to place a unit circuit (cell) used to construct a repetitive circuit portion at the same relative position. An algorithm devised for producing a random circuit is used for routing. It is therefore not guaranteed that the wiring load is the same among the cells constituting a repetitive circuit portion.
The properties of a repetitive circuit portion produced using the design tool are inferior to those of a repetitive circuit portion produced manually by laying out circuit elements thereof with the repetitive circuit portion structured hierarchically. There is therefore an increasing demand for a hierarchical routing method to be implemented in a layout system for a semiconductor integrated circuit according to which the merit of short-term design automatic layout can be exploited while properties that are almost as good as those ensured by manual layout are maintained.
The prior art hierarchical routing method to be implemented in a layout system for a semiconductor integrated circuit and problems associated with the prior art hierarchical routing method will be described in detail later with reference to the drawings.